简介：The aim of this work is to propose a design methodology in order to evaluate and reduce the power consumption of amultistandard decimation and channel selection filter designed to handle three standards: GSM, UMTS and DECT. For this purpose,low power approaches have been evaluated with specific technologies on applications set. The major novelty concerns the evaluation ofthe efficiency of literature methods when applied to a real design having specific constrains and this on different target technologies(ASIC and FPGA).
简介：The aim of this work is to propose a design methodology in order to evaluate and reduce the power consumption of amultistandard decimation and channel selection filter designed to handle three standards: GSM, UMTS and DECT. For this purpose,low power approaches have been evaluated with specific technologies on applications set. The major novelty concerns the evaluation ofthe efficiency of literature methods when applied to a real design having specific constrains and this on different target technologies(ASIC and FPGA).