简介：The design of space-efficient support hardware for built-in self-testing is of great significance in very large scale integration circuits and systems, particularly in view of the paradigm shift in recent times from system-on-board to system-on-chip technology.The subject paper proposes a new approach to designing aliasing-free or zero-aliasing space compaction hardware targeting specifically embedded cores-based system-on-chips for single stuck-line faults extending well-known concept from conventional switching theory, viz. that of compatibility relation as used in the minimization of incomplete sequential machines.
简介：The design of space-efficient support hardware for built-in self-testing is of great significance in very large scale integration circuits and systems, particularly in view of the paradigm shift in recent times from system-on-board to system-on-chip technology.The subject paper proposes a new approach to designing aliasing-free or zero-aliasing space compaction hardware targeting specifically embedded cores-based system-on-chips for single stuck-line faults extending well-known concept from conventional switching theory, viz. that of compatibility relation as used in the minimization of incomplete sequential machines.